An introduction to open-source hardware development
This paper introduces a new trend in hardware design and development — open-source hardware. It defines open-source hardware design terms, features and requirements. It presents FPGA-based platforms as the most suitable for open-source design implementation. It also discusses open-source hardware business models.
Open-source hardware is proposed as a bridge for the technological, educational and cultural gaps between developing and developed countries. Open-source hardware organizations are introduced with statistics of activities. The role of the Internet with respect to hardware openness is introduced.
Open source hardware’s challenges, problems and suggested solutions are described. The paper aims to introduce open-source hardware to the electronic engineering community as an interesting topic of practice, study and research.
1 Introduction and motivation
Open-source software has become an important part of the software development process . A hardware-software analogy allows consideration of open-source hardware. HDLs resemble conventional software programming languages, and programmable implementation platforms resemble general-purpose processors.
An open source phenomenon has several properties that make it interesting for study, and relevant for the discipline of engineering design. Open source eschews traditional engineering concepts such as planning and prototyping in favor of a more organic approach . For instance, the open-source Linux kernel  is one engineering feat that reaches high quality.
The economics of open source defies conventional economic principles, because participants are on volunteer basis. A COCOMO  analysis of widely distributed open-source programs concluded these programs would be valued at one billion U.S. dollars if they were created by conventional means. Open source is a product of the Internet, which enables open-source products to produce tangible results.
The application of open source to hardware brings new benefits to the hardware development process. Open source hardware would reduce development time and design cost. Open source IP cores could be reused, in black box or white box modes. The white box model allows designers to customize a particular core to their own requirements .
2 Open-source hardware definition
Open source hardware is based on publishing all necessary data about the hardware. The design specification, HDL files, simulation test benches, synthesis results, utilization instructions and interfaces to other systems should be documented . The openness of necessary design documentation and its disclosure to the public should be governed by the terms of GPL like licenses .
All information is disclosed for free, according to the terms of GPL-like licenses. The EDA tools used to develop open hardware should also be open. Openness of resources is a must to allow the community to reuse, develop and improve open designs.
3 Open-source hardware implementation
Conventional hardware implementation platforms have various choices. Designs can fit in ASICs, custom silicon, FPGAs , and CPLDs. The question is, what suits open-source hardware design?
The hardware-software analogy points to programmable implementation platforms; hence the answer is programmable logic devices such as PLDs, FPGAs, CPLDs and FPAAs. The analogy between software and hardware implementations applies to different aspects in the development process. Software programs run on general purpose processors, but open hardware designs fit on programmable logic devices.
Software assemblers generate assembly code based on a processor’s instruction set. Hardware synthesis tools generate a netlist of a particular device, using a digital or analog library. Software compilers generate binary code format from an assembly of set of processor’s instruction set. The programming elements of an FPGA generate a bit-stream format from a netlist of device’s component library.
The dynamic reconfigurability  of FPGAs optimizes the performance of hardware designs using real-time dynamic loading and unloading of hardware components on the programmable logic array. This analogy between software and hardware execution and implementation phases helps prove the feasibility of adopting an open-source hardware strategy.
Table 1 — Hardware/software implementation analogy
4 Business models
Open source hardware has a set of business models  that include the following:
Design distribution — Companies can pack sets of designs and sell the distribution just like Linux distributions. The OpenTech CD-ROM  is an example of this method.
Design technical support — Experts can give support for Open designs. Asics.ws  is a company that follows this model by releasing IP cores and charging customers for technical support.
Design implementation — Companies can implement the designs, sell them and pay royalties to original designers, according to their release license.
Releasing — The release of open designs under the control of GPL-compatible licenses can occur whenever a silicon implementation is considered commercially.
5 Open-source hardware roadmap
The open source hardware roadmap  can be divided into three main stages as follows:
Phase I (Primary)
The primary stage objective is to start the development of a set of simple and generic FPGA-based prototyping boards that can be used to test and implement simple open-source IP cores. Open EDA development tools would be used, such that designers can provide feedback to open-source tools developers. The communication between FPGA-based board designers, open IP core designers, and open EDA developers will improve the whole development process of open source- hardware and lead to the next phase.
Phase II (Advanced)
This advanced stage assumes that open-source hardware publicity has taken place. Designers will release advanced open-source designs, including FPGA prototyping boards. The market demand for prototyping boards will boom, which encourages vendors to produce volumes at low prices. The low price exists because the board designs are originally open source, and there is large market demand.
The vendors could produce open-source device programming tools in order to enlarge their market base. The objective of this stage is to allow an open-source hardware user to download open designs from Internet, and implement designs on prototyping boards, just as computer users download open-source software and run it on general-purpose processors in personal computers.
Phase III (Run time configuration)
At this stage, the complexity and density of designs would reach the limitations of conventional programmable logic devices. The dynamic reconfigurability of certain programmable devices is characterized by their ability to reconfigure subsets of their logic and routing resources at runtime, while continuing to operate normally. This intrinsic dynamic reconfiguration results in accommodation of complex and dense designs while maintaining high performance.
The objective of this phase is open-source complex systems design and implementation. This assumes a seamless architecture of system models in which boundaries between software and hardware vanish. For instance, there is an effort to run a Linux kernel as a pure hardware platform that depends mainly on dynamic reconfigurability .
6 High-tech promotion in developing countries
Open-source hardware can contribute to bridging the technological, educational and cultural gaps between developing and developed countries. Open source can help build a high-tech base in these regions due to the following considerations:
Open-source hardware is an open resource for industrial and academic fields.
Lack of high-tech activities and firms.
Lack of expertise in the high-tech field.
Open-source allows interaction with a wide spectrum of experts in high-tech fields all over the world.
HDL designs that address programmable logic devices based implementation platforms can be affordable, as chip manufacturing is beyond economic capabilities.
Open source might help focus the spotlight on high-tech talents and qualifications in developing countries that are hidden due to market constraints.
7 Open-source hardware organizations
This section introduces organizations that adopted the open source hardware model. It provides statistics of activities that run under the Handasa Arabia , OpenCores , and Opencollector  organizations.
The organizational work is a result of volunteer engineers’ efforts to manage the operations and projects under development. An open hardware design of a RISC architecture processor, open RISC1K , is used by some commercial companies that embed the design in their platforms.
The following table (Table 2) could be considered as a performance indicator for open-source hardware. The statistics provide a sample of Handasa Arabia, OpenCores and Opencollector activities.
Table 2 — Open-source organization statistics
8 New computational engines and the Internet
Open-source hardware could produce a new generation of computers and the Internet. Computational engines might change from traditional architectures that are based on software instructions that execute on hardware resources, into algorithms that process hardware functions that load and unload dynamically onto a programmable logic platform.
Future personal computers might be built from FPGA-based boards that contain connectors to the external world. Hardware designers will be able to code modules or cores for specific FPGA computing machines or future computers. The Internet, the fundamental framework for open source designers, might be affected by the concept of dynamic reconfiguration and open-source hardware design. FPGA prototyping boards can be connected to the Internet to act as free computing and debugging machines.
The future might give rise to a new Internet service called “Hardware Computing Resource Protocol” or HCRP. This may enable developers to design their algorithms, which are based on hardware cores, and upload them to these machines to run and implement them. The open source designs, open source computational resources, and global networking introduce a new era of innovative technologies and applications.
9 Challenges and suggested solutions
There are problems that face designers and prevent them from developing open-source hardware.
Cost of EDA tools
Designers can’t afford the cost of EDA tools. The suggested solution is to pursue development of open-source EDA tools and improve them with feedback from the design community. Alliance and gEDA  are good models for open EDA tools.
Hardware manufacturing is relatively expensive. The suggested solution is implementation on FPGA-based prototyping boards or simulation of designs using formal verification techniques.
The suggested solution is the protection of the open designs using GPL-like licenses that reserve rights for original designers, according to particular terms and rules.
Market competition is mainly based on patents and intellectual property that maintain all rights for the originator firm. Companies may oppose aspects of open source that generate alternatives for commercially protected products.
The suggested solution is that companies might take advantage of open source as a way of bridging the gap for time and cost absorbed in R&D. The researchers might find they don’t have to reinvent already existing wheels. Companies may find adoption of an open-source design with large base of customers as a win-win deal. Companies can refine the open-source design with affordable prices and make use of bug fixing provided from the community. The end result is cutting-edge reliable products with affordable prices.
Open source has to build confidence. The suggested solution is that designers produce high quality and completely documented designs. It will be only a matter of time to convince the user community of the credibility of open designs. For instance, the Linux operating system has become reliable and competitive due to efforts exerted to enhance quality and performance from the developing community.
The paper has presented an introduction to open-source hardware as a new trend in the hardware development process. It has defined the requirements for a hardware design to be considered as open. The business models and the phases of an open source hardware roadmap have been presented. The challenges, problems and suggested solutions have been discussed. The paper has introduced the open source hardware to the engineering community as a relevant field of practice, study and future research.
1 Audris Mockus, Roy T. Fielding and James Herbsleb; “A Case Study of Open Source Software Development: The Apache Server.” ACM proceedings of ICSE 2000.
2 Gregor J. Rothfuss; “A Framework for Open Source Projects.” Master’s Thesis in computer science, Department of Information technology, University of Zurich. November 12, 2002, Supervisor, Prof. K. Bauknecht.
3 Linux Operating System.
4 More than a GigaBuck: Estimating GNU/Linux size.
5 Scott A. Hissam, Charles B. Weinstock; “Open Source Software: The Other Commercial Software.” Software Engineering Institute, Carnegie Mellon University, Pittsburgh, PA, USA.
6 Jamil I. Khatib; “Open Hardware Designs for Configurable Computing.”
7 GNU General Public License.
8 Scott Hauck; “The Roles of FPGAs in Reprogrammable Systems.” To appear in Proceedings of the IEEE, Department of Electrical and Computer Engineering, Northwestern University, IL, USA. 9 Michael J. Wirthlin and Brad L. Hutchings; “A Dynamic Instruction Set Computer.” Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA. 10 Opencores Project
11 OpenTech CD ROM
12 Asic.ws Technical Consulting Company
13 Opencores road map
14 Gnu Xilinx Project, Whiphy Computer Systems, UK.
15 Handasa Arabia Organization
16 Opencores Project
17 Opencollector Project
18 Opencores OpenRISC1000
19 Alliance, a free VLSI design system
20 gEDA Project
Mohamed A. Salem is currently a teaching assistant at the School of Engineering at German University of Cairo, Egypt. He was previously a hardware design engineer at Ellipsis Digital Systems.
Jamil I. Khatib is pursuing a master’s degree in technology and innovation management at Brandenburg University in Germany. He was previously a senior FPGA design engineer at Exalt-Technologies (formerly Siemens ICT) in Ramallah, West Bank.
The original version of this article is located at the Handasa Arabia web site. Salem and Khatib are co-founders of that site.
Arab engineers launch open-source organization
8/22/2003 06:55 PM EDT
Original article published at EETimes
Arab engineers launch open-source organization
SANTA CRUZ, Calif. — With a goal of bringing open-source “engineering-systems solutions” to Arab nations and the rest of the developing world, three young Arab engineers have launched a volunteer organization called Handasa Arabia, or “Arabic Engineering,” dedicated to chip design using open-source silicon intellectual property.
The organization is inviting worldwide participation in its projects. The Handasa Arabia web site, which provides information and announcements about open-source hardware, is the launching pad for two ongoing projects: OFOQ, the first Arabic PDA, and Nour, a Bluetooth baseband IP core.
Although the site is focused at present on chip design, the organization said the Web site is intended to provide an outlet for all engineers-including those from biomedical, chemical, aeronautic and other disciplines-to leverage open-source solutions for their designs.One reason to launch the Handasa Arabia Organization, said the founders, is the fact that there are many skilled and educated engineers in the Arab world but few commercial opportunities.
“Universities are teaching chip design, and the program is very competitive to topnotch universities worldwide, but companies in design are rare,” said co-founder Mohamed Salem, a hardware design engineer in Cairo, Egypt. “We have qualifications with no way, or limited chances, to apply our knowledge.”
Salem said he sees Handasa Arabia as “a virtual laboratory and design center for all qualified people who hadn’t had the chance to practice chip design in industrial environments, due to the shortage and lack of high-tech investments in the area.”
“I’d like to see good achievements in the high-tech industry in our world, just like those made by the Western world or the Far East,” said co-founder Jamil Khatib, an FPGA design engineer at Exalt Technologies Ltd., an optical startup in Ramallah, West Bank, that was spun out of Siemens ICT. “I think Handasa Arabia will open opportunities for [Arab] engineers to innovate, and show that their talents are comparable to those in other parts of the world.”
The other co-founder, Mohamed Eldesoky, a systems engineer at Egyptian networking firm TE Data SAE, noted that Handasa Arabia is aimed at helping all developing countries. “Those countries can’t afford the R&D expenses that are usual in the advanced world,” he said. “The R&D budgets in some companies might exceed the income of some very poor developing countries.”
The best way to cultivate chip design in the developing world, all three founders said, is through open-source engineering resources. Khatib has already had extensive involvement in this area. He was a founder of the OpenCores Web site, which is devoted to open-source IP, and he is the producer of OpenTech, a $25 CD-ROM set that contains open-source design automation tools and IP cores.
“Open source provides an easy and cheap platform to start our own projects and discover our abilities,” said Khatib. “It enables us to communicate with engineers and students from all over the world and keeps us up to date with the latest technologies.” Openness, said Salem, is “the most effective methodology to bridge the technological, educational and cultural gaps between developing and developed countries.”
Handasa Arabia projects will use some of the OpenCores IP, Salem noted. But he said that its goals are far broader than those of OpenCores, since they extend beyond open-source silicon IP to solutions for other engineering disciplines.
The group’s mailing list, Salem said, is open to engineers worldwide, as is active participation in projects. He said the organization has members in the United States, Canada, Europe, India, China, Indonesia, Malaysia and other countries. One of the motivations behind the group, Khatib noted, is to foster collaboration among engineers from Arab and other countries.
Handasa Arabia currently maintains three active mailing lists:a general one, and lists for the OFOQ and Nour projects. Project files and specifications for OFOQ and Nour are available at the Web site.
OFOQ is intended to be a PDA-on-a-chip design. Thus far, said Salem, participants have implemented and synthesized a core processor, OpenRisc1k, and are porting the Linux operating system and device drivers to it. The Handasa Arabia Web site describes three versions of the OFOQ, which will use progressively larger CPUs and include more memory and software features, including Koran readers and reciters, an Arabic-English dictionary and a prayer time reminder.
The Nour project seeks to build an open-source Bluetooth baseband controller core. Participants are currently modeling the system as well as writing RTL code for several hardware blocks. A channelized RF link emulation daemon, contributed by an American engineer, may serve as the base link upon which a Nour emulation system can be built.
“Open-source cores are the easiest to design because they only need simulation tools and testing on programmable logic prototype boards,” noted Khatib. “Other techniques require more money, experience, tools and time.”
The organization’s site also carries announcements of open-source EDA and IP developments, along with links to open-source projects. It lists engineering events occurring in the Arab world, including the 15th International Conference on Microelectronics, to be held in Cairo Dec. 9-11, and the 46th IEEE Midwest Symposium on Circuits and Systems, scheduled for Dec. 27-30, also in the Egyptian capital.
Handasa Arabia has yet to attract corporate sponsorship, but is getting recognition from universities, Salem said. “We have several requests to assist senior students while they are developing their graduation projects. As time proves the existence of real work, corporations will be standing by our side.”
CD-ROMs compile open-source EDA, IP
8/14/2003 11:06 PM EDT
CD-ROMs compile open-source EDA, IP
SANTA CRUZ, Calif. — An updated CD-ROM package contains some 190 open-source EDA tools and 130 hardware designs — all for a price of $25. The package, OpenTech version 1.3.0, is a project of OpenCores, an organization devoted to the development of open-source silicon intellectual property (IP).
The OpenTech package is the creation of Jamil Khatib, an FPGA design engineer for Siemens ICT in Rammalla, Palestine. Khatib is one of the founders of the OpenCores web site.
All of the tools and designs on the three OpenTech CDs can be freely downloaded from the web, but tracking them all down would take some time and effort. Khatib said that he initially compiled some open-source EDA tools and hardware designs onto a single CD-ROM for his own use in 2000. He sent postings to some news groups, asking if anyone was interested in a copy.
“In fact, I was not expecting any reply, but I got some requests so I sent the CD-ROMs and started making new releases,” he said. “I got orders from all over the world.” Previous OpenTech releases, he said, have gone to students and working engineers.
The latest version contains three CDs. One contains open-source EDA tools, another contains open-source hardware designs, and a third includes images of the OpenCores site and the CVS utility.
The hardware designs include a number of CPUs, such as Leon-II, Piranha, and risc8; IP cores including DES cryptography, MD5 message digest algorithm, Altera cores, and a logic analyzer core; and a selection of VHDL cores, examples and tutorials. Copies of the emacs editor, Perl, and other utilities are on the same disk as the hardware.
The EDA disk includes tools for analysis, design entry, IC and pc-board layout, PLD design, digital simulation, Spice simulation, synthesis, and verification. Examples include the ChipVault HDL hierarchy tool, gEDA schematic and netlisting tools, Magic IC layout, Icarus Verilog compiler, Jeda verification language, and Alliance VHDL compiler, simulator and synthesizer.
The CD-ROM set can be ordered from the OpenCores OpenTech web site. At this site, engineers can also suggest adding their own tools or designs to the next release, so long as they’re free or open-source.
Open source moves into free hardware
By John G.Spooner | March 28, 2001 — 07:22 GMT (23:22 PST)
A group of hardware developers is trying to bring concepts from the open-source software world to the hardware business.
Engineers around the world, connected via the Internet, are seeking to develop a vast library of freely available hardware designs, similar to how Linux developers and other open-source programmers share intellectual property.
This open-source hardware library — consisting of design elements for processors, memory controllers, peripherals, motherboards and a host of other components — would aid semiconductor start-ups and device manufacturers alike. Instead of investing millions in basic and some times redundant design work, companies would be able to tap the library for the know-how they need, licensing designs for chips and other technology for free.
At the same time, selecting well-designed open-source hardware has the potential to speed development of computing devices, ranging from set-top boxes to network switches. “I started investigating open-source hardware when I was a student in the late ’90s,” Jamil Khatib, an open-source hardware designer and unofficial evangelist for open-source hardware group OpenCores, said in an e-mail interview. “I was wondering why there (was) not open-source hardware, like open-source software, so I started publishing my designs on the Web.
“The open source (process), in general, is the result of contributions from many people around the world about specific design that is open for anyone to contribute (to) and review.”
But choosing to go the open-source hardware route is not as simple as downloading and installing a copy of Linux. Companies using open-source designs still need to integrate the open-source elements into final device designs. This could prove to be a frustrating and costly effort, with no one available to provide direct support for an open-source technology. Potential patent issues also loom. “You see, hardware can never be really free,” said Rudolf Usselmann, a chip designer and active participant in OpenCores. “However, we hope for some cheaper and better-quality hardware. Just look at the unit price of an Intel Pentium chip.”
To get around the manufacturing issue, the open-source community is seeking agreements with companies such as Flextronics, which provides chip manufacturing, engineering and design services. Ultimately, the open-source hardware community would like to create a library so vast that companies could use it to build devices based entirely on open-source designs. But that will take some time.
Open-source hardware owes its life to a number of individuals who, above all else, think it’s fun to design chips and other hardware. The leaders of the movement congregate and share their ideas at focal points on the Internet, such as the OpenCores Web site.
One of the most important efforts now under way is an effort to develop the next OpenRISC processor. The processor — which could be used in Web appliances, factory machines and other Internet-connected devices — is based on a RISC (reduced instruction set) processor core now available as an open-source design. OpenCores plans to integrate a memory controller and a USB controller, among other items, with the new OpenRISC chip. “Big companies spend a lot of money on engineering, not always working very efficiently,” Usselmann said. “In the OpenCores community, we the techies know what we want and we know it best.”
The group is moving to design its next OpenRISC processor with new system-on-a-chip capabilities. A system-on-a-chip (SOC) processor puts a processor core and all the peripheral functions necessary to run a certain hardware device on a single chip. SOC chips are generally used in devices such as set-top boxes, Internet appliances and even some PCs. The new chip would compete with offerings from traditional chipmakers, including National Semiconductor, IBM and even Transmeta, itself an open-source software participant.
Developers, including some working on the new chip, got into open-source hardware for fun. But they quickly became vocal proponents for the open-source way of working. Other members happened on the OpenCore site by chance and signed on. “Basically I was getting bored,” Usselmann said. “I needed something to keep the grey matter going. By accident I came across the OpenCores Web page, and joined in.
“It started as an exercise and to have something to do besides enjoying life. It evolved into lots of fun little projects, without management breathing down your neck, producing cores that people actually find useful.”
Now Usselmann is working to help design the OpenRISC chip and also to help arrange sponsorships for OpenCores projects, both in the form of procuring needed development tools and securing support from contract chip manufacturers, he said.
With new system-on-a-chip designs in the works, along with efforts to create memory controllers, DSP chips and even motherboards, the wealth of technology available at OpenCores promises to snowball. Usselmann alone has posted a number of designs. “So far they have been mostly simple little projects, my current one (the USB 2.0 IP core) is by far the most complex,” he said.
Usselmann’s PIC clone, a version of a popular RISC micro-controller, has been used in several finished chips “because my design is so much faster and allows the users to control what kind and how many peripherals they actually include,” he said.
One of the main challenges developers at OpenCores face is that, despite being able to obtain hardware designs for free, the cost of integrating those hardware bits into a device is still considerable, analysts say. “The big savings would be in licensing fees and royalties on a part, if you ship significant quantities,” said Kevin Krewell, senior analyst at MicroDesign Resources.
At the same time, device makers need support in a range of areas when developing their products. “The hardest part is software support,” Krewell said. The hardware must be made to be compatible with software used in devices.
Despite the potential for new businesses to crop up, it’s unlikely open-source hardware will be as disruptive to hardware makers as open-source software has been to the software industry and players such as Microsoft.
Established chipmakers such as Intel and IBM might not be directly challenged by open-source hardware because their technology, such as Intel’s X86 processor architecture, is protected by a number of closely held patents.
It is possible to create an open-source X86 chip, but without a license for the technology, “I don’t think anyone could hit the open-source world with X86 and survive Intel,” Krewell said.
OpenCores engineers seem unconcerned with competition, however. “We can combine the know-how from all over the world and build and improve on technologies and products,” Usselmann said. “I’m certain that it will become a big success. As we develop more and more cores and address different areas of applications, people are starting to pay more attention to us and what we are doing.”
Usselmann added that dislodging established chipmakers isn’t really the point for open-source hardware. “Just like Intel and AMD can coexist, we can coexist with the big players. We do not intend to compete with the Suns and Ciscos out there.”
But established players would be wise to pay attention to this new hardware-development trend, Khatib said. “The open-source hardware trend will not compete with such companies, but they may need to change their strategies,” he said. When you offer “more options to companies in how they approach the market, that’s a good thing,” Krewell said.
Momentum builds for open-source processors
By Peter Clarke
2/1/2001 08:01 PM EST
Published by EET, Original article at this link
Momentum builds for open-source processors
LONDON — Momentum is slowly building for freely available open-source processors, the semiconductor equivalent of open-source software movements like Linux.
A handful of commercial efforts are experimenting with open-source CPU cores. Contract-manufacturing giant Flextronics, for example, is laying plans to tap into open-source hardware for its ASICs. And both Metaflow Technologies Inc. (La Jolla, Calif.) and IROC Technologies SA (Grenoble, France) are building products using the Leon-1, a Sparc-like open-source processor developed at the European Space Agency’s Technology Center.
Meanwhile, free cores for Bluetooth and the USB 2.0 interface could become available later this year, open-source developers said.
But the movement has its detractors. “Licensees won’t be able to go back to the source” — that is, the engineer who created the design. “That was what killed IP intellectual-property core brokerage in the 1990s,” said Luke Collins, a principal semiconductor analyst at market research firm Gartner Dataquest (Egham, England).
And even EDA companies like Cadence, which is enabling this grass-roots movement by freely licensing tools such as NC-Sim to enthusiasts, believe the free-cores effort is marginal at the moment. “To be honest, there’s little attention paid by the silicon vendors to these open-source blocks,” said Adam Sherer, director of system- and functional-verification IP management at Cadence Design Systems Inc. (San Jose, Calif.).
Nevertheless, say backers, open-source software has scored a dazzling success in Linux, the open-source version of Unix that has swept into the software industry like the Santa Ana winds. Why not open-source cores?
“Open-source IP is a new idea,” said Lior Shtram, an ASIC design manager with Flextronics Semiconductor Inc. in Israel. “In the short term, this concept will have to mature, in terms of studying how to create reliable, well-documented and supported IP using this approach. But open-source software has gone through a similar process and nowadays offers remarkable results.”
Indeed, Flextronics is intrigued enough to consider taking a chance on turning selected cores into ASICs. Shtram said the company is meeting with representatives from the OpenCores organization, a loose but global affiliation of hobbyists, students and young professional engineers, with an eye toward taking some of the hardware cores its members design to silicon.
Enabled by the Internet revolution, OpenCores accomplishes much of its work in e-mail reflectors, chat rooms and newsgroups and through individuals using university or shareware EDA tools. Many of the designers don’t know or care where their collaborators are based. Other open-source hardware projects exist as well, with home bases in Europe, Japan and the United States, although the open-source movement is probably strongest in Europe, where Linux too has its roots.
A step-up in activity over the last year has sparked development of a multitude of open-source cores and ignited industry buzz as the concept wends its way to the world of commercial production.
Late last year Metaflow and IROC announced they were using the European Space Agency’s open-source processor Leon-1 in a system-on-chip (SoC) platform and a demonstration vehicle, respectively. Metaflow, a subsidiary of STMicroelectronics Inc., uses Leon as the heart of an SoC development system called Implosion, which it launched in December. And Leon-1 is the basis of IROC Technologies’ ROC-S81 32-bit RISC processor, designed to protect space-borne electronics systems from soft errors.
Leon was designed for the space agency’s ERC32 platform for space electronics by Jiri Gaisler, who has just left his job at the agency’s Technology Center in Noordwijk, Netherlands. ERC32 is based on a commercial Sparc 32-bit processor in packaged-chip form. But because the agency knew it would need to embed Sparc RISC processors in SoCs, it opted to develop its own hardware core.
To help increase the availability of development tools, operating systems and application software — and thereby reduce its own costs — the Technology Center, called Estec, decided to spread the architecture widely by making it available under an open-source agreement. The result is Leon-1, an implementation of the IEEE’s proposed P1754 standard for a Sparc V8 microprocessor. Leon-1 source code is distributed under the GNU Lesser General Public License; links to the source code, software and other developer’s resources can be found at the Estec Web site.
Leon-1 evolved throughout 2000 and has reportedly been implemented in several FPGA projects by enthusiasts around the world. “Leon-1 2.2 now has Amba AHB and APB on-chip buses,” said Gaisler, referring to the ARM Ltd. microprocessor buses. “This makes it very much simpler to add peripherals.”
Gaisler, whose new company, Gaisler Research (Goteborg, Sweden), will provide consulting services to the European Space Agency on the ERC32 project, said that “five or six FPGA versions of Leon-1 have been built already,” emphasizing one of the advantages of open-source: that multiple developers can share debugging costs and build confidence in the functional integrity of the source code.
Moreover, said Gaisler, “We’re expecting samples of the Leon 2.1-FT in February.” This fault-tolerant version is being built in a 0.35-micron CMOS process at Atmel Corp.’s foundry at Rousset, France. Gaisler said the designation “FT” indicates the design has been augmented with European Space Agency fault-tolerance structures intended to make commercial CMOS fit to sustain radiation effects, in order to allow SoC deployment in space.
As for the commercial uses of Leon-1, Gaisler described Metaflow’s implementation “as an ARM processor-core replacement. Rather than paying a lot of money to ARM you get a core for free — but you have to be prepared to spend a lot of your own engineering time on it,” he cautioned.
IROC, meanwhile, is awaiting silicon for its Leon-based implementation from an unidentified foundry in the next few weeks. IROC adds protective circuitry for both logic and memories, a strategy the company claimed is unique, to guard against cosmic-radiation-induced soft errors, crosstalk effects and even signal-timing errors, said Michael Nicolaidis, chief technology officer.
He said IROC picked the Leon as a demonstration vehicle because it was freely available. The company now intends to apply the scheme to other processors, he said, and has a contract to add its form of robustness to a 16-bit microcontroller. IROC has also started negotiations on licensing the ROC-S81, Nicolaidis said.
Perhaps a bigger coup for the open-source core movement is the potential backing of Flextronics Semiconductor (Sunnyvale, Calif.). That company is looking to mine some of the cores, working or in development, generated by the OpenCores developers as the possible basis for ASICs. The group’s Web site lists everything from 32- and 8-bit RISC cores through cryptography devices to standard peripherals, I/O controllers and memories. Usually the OpenCores designers are restricted to blowing their designs into FPGAs, since it’s all they can afford.
“We’ve certainly taken a look at OpenCores,” said Ralph Waggitt, vice president of marketing at Flextronics Semiconductor, a company known for its ability to retarget FPGAs to ASIC technology. Formerly called Orbit Semiconductor, it is a subsidiary of Flextronics International Ltd., a manufacturing-services company based in Singapore.
“We’re not in the IP business,” Waggitt said. “We’re in the silicon business and we have some reservations. We’re trying to understand how OpenCores works and what the responsibilities and liabilities might be.”
Shtram said the OpenCores project would likely involve providing a number of development tools to individual OpenCores designers, and also supplying engineering time to prepare the cores for manufacture.
“We’re talking about a one-year schedule,” said Shtram. “We understand that just taking cores directly from OpenCores will not work; much hard work should be put in in order to enable the creation of reliable, tested and supported IP within this framework. And we are ready to put that effort and those resources into the project.”
Flextronics intends to “identify interesting cores within the group, and support the development process of these cores with funds, work and a test ASIC,” Shtram said. “In this way developers within OpenCores could achieve working silicon that implements their IP, and we achieve the experience needed to create a working ASIC using the IP and a demonstration ASIC to show our customers.”
Shtram would like to see more companies sign on to explore the possibilities inherent in the open-core movement. “At this stage more companies joining this game will add their experience and help the speed of the maturing process,” said Shtram. “It’s a good place to have cooperation. We wouldn’t want to be the only player. It would be good if other companies would get involved.”
Barriers to success
But analyst Collins is among those who foresee business problems for any companies setting foot in open-source terrain. “Building a business model around a core which is not your own and from which you are decoupled by one or more layers is going to raise the barriers to success,” Collins said.
Though the idea of obtaining a core for free might be appealing, Collins pointed out that the cost of a major SoC project usually far exceeds the cost of licensing intellectual property, once you figure in engineering time and mask sets that cost up to half a million dollars for deep-submicron silicon. In his view, it is not worth jeopardizing a project for the small amount saved on a free core that comes with no reliable warranties and nobody to sue if things go wrong.
Indeed, one open-source developer, Rudolf Usselmann, adds heavy disclaimers to the designs he posts on the OpenCores site, along the lines of “I have no idea if implementing this core will or will not violate patents, copyrights or cause any other type of lawsuits. I provide this core as is, without any warranties.”
Of course, if all one needs is a processor and a C compiler — perhaps to build a system in an FPGA — then an open-source core might be just the ticket, argued Usselmann, who spent 15 years working in Silicon Valley before entering semiretirement in his mid-30s. Usselmann has developed an 8-bit data, 12-bit instruction word microcontroller compatible with the PIC16C57 from Microchip Technologies Inc. (Chandler, Ariz.) and several crypto-processor cores. Usselmann makes the source code available for the PIC-like device.
A former Sun Microsystems Inc. designer, Usselmann said he developed his PIC core “as an exercise for myself — I did the whole thing in about one night.” He said he is now working on a USB 2.0-compliant interface core.
Usselmann praised the OpenCores group for its freewheeling atmosphere. “Being an open organization, we don’t have marketing and management people forcing their ideas on us,” he said. “We can let our imaginations fly and do some neat things.”
Another designer tinkering with open cores is Jamil Khatib, by day an electronics designer for Siemens ICT (Rammala, Palestine) but on his own time active in the open-source community. Khatib said he began looking for free hardware cores on the Internet while still a university student in the mid-1990s and, when he couldn’t find any, started writing and publishing his own.
“My first project was a FIFO,” he said. “Why shouldn’t we have generic hardware, not just for CPUs but all sorts of hardware?”
Khatib later worked on the Freedom-CPU, a 64-bit superpipelined RISC microprocessor that is being developed by a team united in a coalition that describes itself as “a bunch of people that speak about CPU design on a mailing list where the owner has disappeared.” The University of Paris is one hot spot of Freedom-CPU activity, and much of the impetus for the ambitious 64-bit processor design comes from European engineers.
F-CPU has just released VHDL and support files for the ROP2 execution unit that is at the heart of this single-instruction, multiple-data (SIMD) device. But there are still many more building blocks to be designed, and therefore a great deal of testing to be done.
Far to close
“This is a problem. It is very hard to get a group to close a design,” said Khatib. “Sometimes it’s just easier for one person to work at something, make the decisions and get it done. I’ve just started work on a Bluetooth baseband core like that.”
Whether lone wolf or part of a design team, core developers need EDA tools to bring their designs to fruition. Sherer at Cadence confirmed that his company has made a limited number of NC-Sim licenses available at no cost or at heavily discounted charges to OpenCores and made a similar offer to the Freedom-CPU group.
“Cadence has been operating as an IP facilitator in the market for some time,” Sherer said. “OpenCores is an interesting case. It’s an open-source environment that was looking to move to a more sophisticated tool set. So we’ve provided NC-Sim and VHDL packaging tools.”
Sherer said Cadence viewed these groups as similar to educational establishments, and not as competitors to its mainstream customers.
“There’s a big gap between developing and delivering a complete virtual component and developing a simulation model,” he said. “To get an IP core into the market is not that large an effort. You get hold of a specification for something and develop the core. But it’s a very large gap to get from there to providing a tier-one company with a core, which is where the revenue is.”
In Sherer’s view, there’s good reason to provide such groups with EDA tools for a company like Cadence that wants to keep its finger on the pulse of the industry. Even if the particular cores an open-source group is working on today do not prove to be significant, he said, the individuals involved could move on to bigger things. Like Linux developers before them, they could turn into next-generation entrepreneurs with an impact in setting standards in the IP-cores community.
Sherer wants these maverick engineers to be familiar with Cadence and to help make Cadence EDA tools the standard in the IP community.
OpenIPCore Hardware General Public License “OHGPL”*
*Draft Version 0.20-15092000 September 2000*
Copyright (C) 2000 OpenIPCore Organization.
Everyone is permitted to copy and distribute and modify this document
under the terms of the GNU Free Documentation License.
The preamble is part of the license and the license and its preamble can
not be split out.
*SYSTEM: * Is any thing that works or supposed to work to do some
operations depending on some specific inputs and produce some results.
*HARDWARE DESIGN:* (The terms HARDWARE DESIGN and DESIGN can be used
interchangeably in the license)
Is any work that defines, describes or simulates a system or part of a
system that could be physically implemented. This includes but not
limited to, system architectures, design ideas, design description,
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portion of it as is. Any time you copy or distribute this design you
have to provide all of the source files and documentations that came
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Any attempt otherwise to copy, modify, sublicense or distribute the
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A. How to Apply These Terms to Your New Hardware designs:
1. you can include this license with your design description and design
and fabrication files 2. You can place a notice in the files about the
use of this license.
B. Notes and Remarks:
1. This license is based on copyright so there is no restriction on the
implementation of the hardware design. 2. You can provide a notice about
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1. Created on 8 October 1999 by Jamil Khatib.
2. Revision 0.16 on 12 October 1999 by Jamil Khaitb
– – Revised by several related mailing lists.
– – Preamble was added with set of definitions
– – Name was changed to OpenIP Hardware General Public License “OHGPL”
3. Revision 0.16 on 15 October 1999 by Jamil Khatib
– – Updated the license with the comments mentioned in the mailing list
upto 14 October, 1999.
4. Revision 0.17 on 26 October 1999 by Jamil Khatib
– – Updated item 5 so that the designs description can be sold.
5. Revision 0.2 on 15 September 2000 by Jamil Khatib
– – Major rewrite to the license to cover up to date issues.
– – Item 6 is used to provide the compatibility with the LGPL.