Momentum builds for open-source processors
By Peter Clarke
2/1/2001 08:01 PM EST
Published by EET, Original article at this link
Momentum builds for open-source processors
LONDON — Momentum is slowly building for freely available open-source processors, the semiconductor equivalent of open-source software movements like Linux.
A handful of commercial efforts are experimenting with open-source CPU cores. Contract-manufacturing giant Flextronics, for example, is laying plans to tap into open-source hardware for its ASICs. And both Metaflow Technologies Inc. (La Jolla, Calif.) and IROC Technologies SA (Grenoble, France) are building products using the Leon-1, a Sparc-like open-source processor developed at the European Space Agency’s Technology Center.
Meanwhile, free cores for Bluetooth and the USB 2.0 interface could become available later this year, open-source developers said.
But the movement has its detractors. “Licensees won’t be able to go back to the source” — that is, the engineer who created the design. “That was what killed IP intellectual-property core brokerage in the 1990s,” said Luke Collins, a principal semiconductor analyst at market research firm Gartner Dataquest (Egham, England).
And even EDA companies like Cadence, which is enabling this grass-roots movement by freely licensing tools such as NC-Sim to enthusiasts, believe the free-cores effort is marginal at the moment. “To be honest, there’s little attention paid by the silicon vendors to these open-source blocks,” said Adam Sherer, director of system- and functional-verification IP management at Cadence Design Systems Inc. (San Jose, Calif.).
Nevertheless, say backers, open-source software has scored a dazzling success in Linux, the open-source version of Unix that has swept into the software industry like the Santa Ana winds. Why not open-source cores?
“Open-source IP is a new idea,” said Lior Shtram, an ASIC design manager with Flextronics Semiconductor Inc. in Israel. “In the short term, this concept will have to mature, in terms of studying how to create reliable, well-documented and supported IP using this approach. But open-source software has gone through a similar process and nowadays offers remarkable results.”
Indeed, Flextronics is intrigued enough to consider taking a chance on turning selected cores into ASICs. Shtram said the company is meeting with representatives from the OpenCores organization, a loose but global affiliation of hobbyists, students and young professional engineers, with an eye toward taking some of the hardware cores its members design to silicon.
Enabled by the Internet revolution, OpenCores accomplishes much of its work in e-mail reflectors, chat rooms and newsgroups and through individuals using university or shareware EDA tools. Many of the designers don’t know or care where their collaborators are based. Other open-source hardware projects exist as well, with home bases in Europe, Japan and the United States, although the open-source movement is probably strongest in Europe, where Linux too has its roots.
A step-up in activity over the last year has sparked development of a multitude of open-source cores and ignited industry buzz as the concept wends its way to the world of commercial production.
Late last year Metaflow and IROC announced they were using the European Space Agency’s open-source processor Leon-1 in a system-on-chip (SoC) platform and a demonstration vehicle, respectively. Metaflow, a subsidiary of STMicroelectronics Inc., uses Leon as the heart of an SoC development system called Implosion, which it launched in December. And Leon-1 is the basis of IROC Technologies’ ROC-S81 32-bit RISC processor, designed to protect space-borne electronics systems from soft errors.
Leon was designed for the space agency’s ERC32 platform for space electronics by Jiri Gaisler, who has just left his job at the agency’s Technology Center in Noordwijk, Netherlands. ERC32 is based on a commercial Sparc 32-bit processor in packaged-chip form. But because the agency knew it would need to embed Sparc RISC processors in SoCs, it opted to develop its own hardware core.
To help increase the availability of development tools, operating systems and application software — and thereby reduce its own costs — the Technology Center, called Estec, decided to spread the architecture widely by making it available under an open-source agreement. The result is Leon-1, an implementation of the IEEE’s proposed P1754 standard for a Sparc V8 microprocessor. Leon-1 source code is distributed under the GNU Lesser General Public License; links to the source code, software and other developer’s resources can be found at the Estec Web site.
Leon-1 evolved throughout 2000 and has reportedly been implemented in several FPGA projects by enthusiasts around the world. “Leon-1 2.2 now has Amba AHB and APB on-chip buses,” said Gaisler, referring to the ARM Ltd. microprocessor buses. “This makes it very much simpler to add peripherals.”
Gaisler, whose new company, Gaisler Research (Goteborg, Sweden), will provide consulting services to the European Space Agency on the ERC32 project, said that “five or six FPGA versions of Leon-1 have been built already,” emphasizing one of the advantages of open-source: that multiple developers can share debugging costs and build confidence in the functional integrity of the source code.
Moreover, said Gaisler, “We’re expecting samples of the Leon 2.1-FT in February.” This fault-tolerant version is being built in a 0.35-micron CMOS process at Atmel Corp.’s foundry at Rousset, France. Gaisler said the designation “FT” indicates the design has been augmented with European Space Agency fault-tolerance structures intended to make commercial CMOS fit to sustain radiation effects, in order to allow SoC deployment in space.
As for the commercial uses of Leon-1, Gaisler described Metaflow’s implementation “as an ARM processor-core replacement. Rather than paying a lot of money to ARM you get a core for free — but you have to be prepared to spend a lot of your own engineering time on it,” he cautioned.
IROC, meanwhile, is awaiting silicon for its Leon-based implementation from an unidentified foundry in the next few weeks. IROC adds protective circuitry for both logic and memories, a strategy the company claimed is unique, to guard against cosmic-radiation-induced soft errors, crosstalk effects and even signal-timing errors, said Michael Nicolaidis, chief technology officer.
He said IROC picked the Leon as a demonstration vehicle because it was freely available. The company now intends to apply the scheme to other processors, he said, and has a contract to add its form of robustness to a 16-bit microcontroller. IROC has also started negotiations on licensing the ROC-S81, Nicolaidis said.
Perhaps a bigger coup for the open-source core movement is the potential backing of Flextronics Semiconductor (Sunnyvale, Calif.). That company is looking to mine some of the cores, working or in development, generated by the OpenCores developers as the possible basis for ASICs. The group’s Web site lists everything from 32- and 8-bit RISC cores through cryptography devices to standard peripherals, I/O controllers and memories. Usually the OpenCores designers are restricted to blowing their designs into FPGAs, since it’s all they can afford.
“We’ve certainly taken a look at OpenCores,” said Ralph Waggitt, vice president of marketing at Flextronics Semiconductor, a company known for its ability to retarget FPGAs to ASIC technology. Formerly called Orbit Semiconductor, it is a subsidiary of Flextronics International Ltd., a manufacturing-services company based in Singapore.
“We’re not in the IP business,” Waggitt said. “We’re in the silicon business and we have some reservations. We’re trying to understand how OpenCores works and what the responsibilities and liabilities might be.”
Shtram said the OpenCores project would likely involve providing a number of development tools to individual OpenCores designers, and also supplying engineering time to prepare the cores for manufacture.
“We’re talking about a one-year schedule,” said Shtram. “We understand that just taking cores directly from OpenCores will not work; much hard work should be put in in order to enable the creation of reliable, tested and supported IP within this framework. And we are ready to put that effort and those resources into the project.”
Flextronics intends to “identify interesting cores within the group, and support the development process of these cores with funds, work and a test ASIC,” Shtram said. “In this way developers within OpenCores could achieve working silicon that implements their IP, and we achieve the experience needed to create a working ASIC using the IP and a demonstration ASIC to show our customers.”
Shtram would like to see more companies sign on to explore the possibilities inherent in the open-core movement. “At this stage more companies joining this game will add their experience and help the speed of the maturing process,” said Shtram. “It’s a good place to have cooperation. We wouldn’t want to be the only player. It would be good if other companies would get involved.”
Barriers to success
But analyst Collins is among those who foresee business problems for any companies setting foot in open-source terrain. “Building a business model around a core which is not your own and from which you are decoupled by one or more layers is going to raise the barriers to success,” Collins said.
Though the idea of obtaining a core for free might be appealing, Collins pointed out that the cost of a major SoC project usually far exceeds the cost of licensing intellectual property, once you figure in engineering time and mask sets that cost up to half a million dollars for deep-submicron silicon. In his view, it is not worth jeopardizing a project for the small amount saved on a free core that comes with no reliable warranties and nobody to sue if things go wrong.
Indeed, one open-source developer, Rudolf Usselmann, adds heavy disclaimers to the designs he posts on the OpenCores site, along the lines of “I have no idea if implementing this core will or will not violate patents, copyrights or cause any other type of lawsuits. I provide this core as is, without any warranties.”
Of course, if all one needs is a processor and a C compiler — perhaps to build a system in an FPGA — then an open-source core might be just the ticket, argued Usselmann, who spent 15 years working in Silicon Valley before entering semiretirement in his mid-30s. Usselmann has developed an 8-bit data, 12-bit instruction word microcontroller compatible with the PIC16C57 from Microchip Technologies Inc. (Chandler, Ariz.) and several crypto-processor cores. Usselmann makes the source code available for the PIC-like device.
A former Sun Microsystems Inc. designer, Usselmann said he developed his PIC core “as an exercise for myself — I did the whole thing in about one night.” He said he is now working on a USB 2.0-compliant interface core.
Usselmann praised the OpenCores group for its freewheeling atmosphere. “Being an open organization, we don’t have marketing and management people forcing their ideas on us,” he said. “We can let our imaginations fly and do some neat things.”
Another designer tinkering with open cores is Jamil Khatib, by day an electronics designer for Siemens ICT (Rammala, Palestine) but on his own time active in the open-source community. Khatib said he began looking for free hardware cores on the Internet while still a university student in the mid-1990s and, when he couldn’t find any, started writing and publishing his own.
“My first project was a FIFO,” he said. “Why shouldn’t we have generic hardware, not just for CPUs but all sorts of hardware?”
Khatib later worked on the Freedom-CPU, a 64-bit superpipelined RISC microprocessor that is being developed by a team united in a coalition that describes itself as “a bunch of people that speak about CPU design on a mailing list where the owner has disappeared.” The University of Paris is one hot spot of Freedom-CPU activity, and much of the impetus for the ambitious 64-bit processor design comes from European engineers.
F-CPU has just released VHDL and support files for the ROP2 execution unit that is at the heart of this single-instruction, multiple-data (SIMD) device. But there are still many more building blocks to be designed, and therefore a great deal of testing to be done.
Far to close
“This is a problem. It is very hard to get a group to close a design,” said Khatib. “Sometimes it’s just easier for one person to work at something, make the decisions and get it done. I’ve just started work on a Bluetooth baseband core like that.”
Whether lone wolf or part of a design team, core developers need EDA tools to bring their designs to fruition. Sherer at Cadence confirmed that his company has made a limited number of NC-Sim licenses available at no cost or at heavily discounted charges to OpenCores and made a similar offer to the Freedom-CPU group.
“Cadence has been operating as an IP facilitator in the market for some time,” Sherer said. “OpenCores is an interesting case. It’s an open-source environment that was looking to move to a more sophisticated tool set. So we’ve provided NC-Sim and VHDL packaging tools.”
Sherer said Cadence viewed these groups as similar to educational establishments, and not as competitors to its mainstream customers.
“There’s a big gap between developing and delivering a complete virtual component and developing a simulation model,” he said. “To get an IP core into the market is not that large an effort. You get hold of a specification for something and develop the core. But it’s a very large gap to get from there to providing a tier-one company with a core, which is where the revenue is.”
In Sherer’s view, there’s good reason to provide such groups with EDA tools for a company like Cadence that wants to keep its finger on the pulse of the industry. Even if the particular cores an open-source group is working on today do not prove to be significant, he said, the individuals involved could move on to bigger things. Like Linux developers before them, they could turn into next-generation entrepreneurs with an impact in setting standards in the IP-cores community.
Sherer wants these maverick engineers to be familiar with Cadence and to help make Cadence EDA tools the standard in the IP community.